Design of Highly-Accurate and Hardware-Efficient Spiking Neural Networks

Spiking neural networks (SNNs) have emerged as a promising alternative to conventional artificial neural networks (ANNs) for energy efficient design. The rate encoded computation in SNNs utilizes a number of spikes in a time window to encode information. In a similar but different scheme, stochastic computing (SC) encodes binary numbers into and operates on random binary bit streams. In this article, we first propose a hardware-efficient design of stochastic SNNs that attains a high accuracy. As a network becomes more complex or the number of neurons increases, memory usage tends to grow exponentially. Inspired by the notion of binarized neural networks (BNNs), we further propose the design of a weight-binarized SNN (WB-SNN) to reduce the stringent requirement in memory usage in SNNs. Both designs take advantage of a priority encoder to transform the spikes between layers of neurons into index-based signals. In this way, it mitigates the issue of requiring significant hardware resources for a relatively low information density. Additionally, a WB-SNN based convolutional neural network (CNN) is designed for the recognition task of larger datasets. An implementation on field programmable gate arrays (FPGAs) for the Modified National Institute of Standards and Technology (MNIST) image recognition dataset shows that the stochastic SNN design achieves a higher accuracy with smaller hardware compared to other SNNs. Validated by using a multi-layer-perceptron and a CNN on the MNIST and CIFAR-10 datasets, respectively, the WB-SNN achieves a significant saving in memory with only a limited accuracy loss compared with its SNN and BNN counterparts.