A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications

A 14-bit, 6.7 MS/s successive-approximation-register (SAR) A/D converter (ADC) is presented with on-chip autocalibration. An all-digital calibration algorithm with only two extra half-unit capacitors in capacitive DAC (CDAC) enables the ADC to correct itself from mismatch errors. We introduce digital heavy on-the-fly autocalibration, with novel reuse mechanism of existing capacitors, which deliver analog-precision error-correction yielding superior integral-nonlinearity (INL) and spurious free dynamic range (SFDR) at lowest area. The design is limited by thermal noise and not by mismatch error. A self-shut mechanism in dynamic comparator saves power consumption. A 0.018 mm² test chip in a 65-nm CMOS process consumes $98~\mu $ W power. The calibration improves the INL of the ADC from >20 least significant bit (LSB) to <2.9 LSB. The design achieves a minimum effective number of bit (ENOB) of 11.3-bit with FoM ${}_{W}$ of 5.8 fJ/conv-step and FoM ${}_{S}$ of 175 dB at an area efficiency (AE) of $7.2~\mu $ m²/code.