A Sub-10 μ s In-Memory-Search Collision Detection Accelerator Based on RRAM-TCAMs

Collision detection can account for over 90% of the total calculation time in motion planning, which makes it critical to optimize the collision detection process. Previous hardware accelerators can hardly maintain fast computation speed for real-time collision detection while supporting a large roadmap. In this work, we present a novel in-memory-search accelerator. hasub-10 μJs time for collision detection in 800 MB scale roadmaps with 100,000 edges. Such accelerator leverages an in-memory-search architecture that can perform search operation in massively parallel manner with low energy consumption. It is powered by ternary content-addressable memories (TCAMs) based on large-scale nonvolatile resistive random-access memory (RRAM) arrays, which not only store a large roadmap on chip, but also perform look-up table function in a single clock cycle to accelerate collision detection by combining with the unique logic encoding scheme. Importantly, the RRAM-based TCAM eliminates the need for extensive data transfer between memory and computing units during collision detection, leading to significant energy and delay saving. As the pioneering TCAM-based in-memory-search accelerator for collision detection, the structure achieves 210.2,225× times speedup compared with previous ASIC-based accelerators, and more than 33,879 times speedup compared with CPU-based collision detection. Such accelerator well exceeds the speed requirement for collision detection (<1 ms), and is suitable for a number of applications such as robot motion planning in dynamic environment, animation, machining and manufacturing.