4X5 Dynamic Random Access Memory Stores Data Using Digital Circuits

This paper mainly focuses on building a 4X5 DRAM using logic circuits from transistor logic to devices. It concentrates on building a DRAM using a transistor that consumes less power, less area and proper functionality. Designing a DRAM is modeled using Cadence Virtuoso from schematics to layout. In schematics the cells are constructed using transistors, the cells are 2X4 decoder, 2X1 multiplexer, 1-BIT storage, read and write controller, 3 XOR gates and tristate buffer. All the cells are connected according the 4X5 DRAM architecture which is further discussed in the paper.