FPGA-based Voltage Balancing Control for MMC

The voltage balancing control of submodules’ (SM) capacitors is the key in modular multilevel converter-based high-voltage direct-current (MMC-HVDC) transmission system, where the sorting link for the SMs’ capacitor voltage has relatively high time and space complexity. According to the principle of the bitonic sorting algorithm, parallelism and pipeline technique, a parallel sorting network suitable for field programmable gate array (FPGA) is designed in this paper based on the idea of staged-calculation, which can reduce the time complexity of the voltage balancing control. Secondly, according to the characteristics for the voltage data of SMs’ capacitors and the sorting network, the data format input into the sorting network is designed. And the sorting network is designed to adapt to changes in the number of SMs and can be time-sharing reused, based on the ideas of redundant calculation and logical reuse, which can reduce the space complexity of the voltage balancing control. Finally, the proposed voltage balancing control is implemented based on FPGA, and its effectiveness is verified through in-the-loop simulation experiments based on RTDS.