A 9.2–18-GHz Sub-3.5-dB NF CMOS Low Noise Amplifier Using Current-Reuse Stacked Inverter With Inductive Series Peaking

In this paper, we introduce a novel wideband CMOS low noise amplifier (LNA) that employs a current-reuse stacked inverter (CRSI) in conjunction with advanced inductive peaking to significantly enhance noise performance and gain flatness across an ultrawide frequency range. The proposed CRSI integrates two resistive feedback inverters with source-degeneration inductors in a current-reuse configuration. This unique topology not only boosts the transconductance but also aligns the input impedance with the optimal impedance for the minimum noise figure (NF) through precise tuning of the source-degeneration inductors. By incorporating an input-matching network and an output-matching network, simultaneous input and noise matching achievements—resulting in reduced return loss and minimized NF—and a high-pass filter (HPF) configuration for suppressing low-frequency output are realized, respectively. Our meticulously engineered multiple inductive peaking inductors—comprising inter-stage and inter-cell matching inductors—are strategically optimized to maximize gain and enhance NF over the entire operating frequency range of 9.2 to 18 GHz. Fabricated using 65-nm CMOS technology, the proposed LNA occupies a total chip area of 0.38 mm2, including input and output testing pads. Measured results show that the LNA achieves a peak gain of 26.6 dB and a minimum NF of 2.3 dB within the frequency range of 9.2 to 18 GHz. The power consumption of the LNA is 11.4 mW at 2 V, achieving a competitive figure of merit (FoM) among recently reported wideband CMOS LNAs.