Investigating PSN and GBN Induced Jitter at Different Stages of a Chain of CMOS Inverters

This paper presents novel observations on power supply noise (PSN) and ground-bounce noise (GBN) induced jitter in a chain of CMOS inverters. The proposed approach uses semi-analytical expressions to estimate jitter based on small-signal noise transfer function for $N^{th}$ inverter stage. It uses slope-based jitter estimation technique. Estimated jitter due to the presence of only PSN or GBN shows a zig-zag increase or decrease pattern of jitter with number of stages, whereas it remains almost consistent when both noise sources are present in the circuit. These observations are validated with the results obtained from semi-analytical approach and measurement setup.