Design of Low Power High Speed Flipflop using 18nm FinFET Technology

A flip-flop is a type of sequential logic circuit used primarily for storing digital data in various digital devices, thereby improving the functionality of digital circuits. The conventional flip-flops suffers from high power consumption and also have higher transistor count. This paper introduces a novel flip-flop architecture designed for energy efficiency. The proposed flip-flop demonstrates high reliability while maintaining low power consumption. The architecture was simulated employing 18 nm finFET technology with a power supply of 0.7 V. The proposed flip-flop design aims to minimise power consumption and improve operational speed. Reducing the number of PMOS transistors may enhance the efficiency of the proposed design. A single clock serves as the primary interface for the clock signal to enter the circuit. The proposed designs have been executed using 18 nm finFET chip technology. This study performs a PVT assessment to determine the reliability of the flip-flop. The proposed flip-flop exhibits a minimum power reduction of 9.22% compared to existing flip-flops, a minimum leakage power reduction of 17.48%, and a minimum clock-to-output delay reduction of 68.37%.