Design and Analysis of Low Power High Speed Multi Bit Flip-Flop using Various Design Logics

Power dissipation accounts for high-performance digital systems in the deep sub-micron region. As a result, power within compact systems is vital. A Multi-bit flip-flop(MBFF) is a sequential logical circuit essential for storing digital information in numerous digital gadgets, enhancing the general performance of digital circuits. Traditional MBFFs experience significant power usage and require a greater number of transistors. This paper uses conventional CMOS to investigate four distinct kinds of MBFF: transmission gates, pass transistors, and GDI gates. According to simulation findings, the suggested GDI-based MBFF has the lowest PDP. The number of transistors needed to create an MBFF is lowered in PTL compared to others. T-SPICE is used to simulate the circuits in PTM 16 nm manufacturing technology.The simulation is performed regarding the delay, power, as well as Power Delay Product (PDP) at supply voltages of 0.8 V, & 1 V.