Machine Learning-Based Fault Detection in VLSI Circuits

This paper addresses the growing complexity of electronic devices and the need for efficient fault detection in VLSI circuits. Traditional fault detection methods are often inaccurate and time-consuming, motivating the use of artificial intelligence techniques. The paper proposes a deep learning-based model for detecting stuck-at faults in digital VLSI circuits. Our model leverages an Autoencoder algorithm to compress features and mitigate the search space explosion problem, achieving a range of accuracies of 75.3% to 99.9% for various ISCAS'85 benchmark circuits. The model incorporates ATPG tools such as the ATALANTA tool for generating test patterns and corresponding fault-free responses using the FAN algorithm. These test patterns are preprocessed to be used as a dataset where the Autoencoder algorithm classifies faulty and non-faulty responses based on their reconstruction error. These approaches demonstrate the potential of deep learning in improving the efficiency and accuracy of fault detection in digital VLSI circuits.