A 37.5fs-rms Jitter and −254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset

The revolution of communication protocols beyond 5G raises more and more stringent phase noise (PN) requirements on the local oscillator (LO) [1]. Sampling PLLs (SPLLs) have gained widespread adoption due to their effective suppression of in-band phase noise. Digital-to-time converters (DTCs) are widely used in fractional-N SPLLs to compensate the quantization noise generated by the Delta-Sigma Modulators (DSMs). To achieve a rms jitter below 50fs, reducing DTC range and delay time is urgently desired. With a reduced DTC range and delay offset (which corresponds to the mean value of the DTC code), DTC integral nonlinearity (INL) decreases and its effective delay time is shortened, therefore the nonlinearity-introduced noise-folding is suppressed and DTC thermal noise is reduced. A modified multi-modulus divider (MMD) with novel DSM is utilized in [2] to cut the output range of DSM by half, achieving an 83fs-rms jitter. Ring oscillator in [3] and phase interpolator in [4] are utilized as DTC coarse conversion which suffer from extra noise and nonlinearity, while an LC-based coarse DTC used in [5] occupies a larger area due to the inductor array. This work presents a fractional-N PLL with reference-phase-selection (RPS) and complementary-DTC architecture which achieves 8× DTC range reduction and zero DTC delay offset. This improves the DTC INL and reduces the DTC noise contribution. Furthermore, a clock-based reference-spur cancellation technique is proposed to suppress the voltage disturbance at the sampling phase detector (SPD) output. Combined with a dual-core VCO, the 15-GHz SPLL demonstrates a 37.5fs-rms jitter, −69.1dBc reference spur, and −254.1dB FoM.