A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving −65.7dBc Fractional Spur and 154fs Integrated Jitter

Low-jitter and low-spur frequency synthesizers play pivotal roles in highperformance wireless transceivers and FMCW radars. To achieve an ultra-low fractional spur, a digital-to-time converter (DTC) is utilized to cancel quantization errors from the delta-sigma modulator (DSM). However, DTC non-linearity can still induce significant fractional spurs, degrading the PLL spectral purity and increasing integrated jitter. As illustrated in Fig. 1 (top), the DTC in the reference path generates fractional spurs mainly from DTC 2nd and 3rd non-linearity. Probability-Density Shaping (PDS) [1] uses a special dither to eliminate fractional spurs (< -60dBc) by randomizing 2nd and 3rd-order non-linearities but it increases in-band phase noise, especially in low-jitter PLLs. Alternatively, the pseudodifferential DTC technique [2] suppresses the even-mode non-linearity of DTCs. It requires fewer DPD lookup tables, yet DTCs cannot remove odd-mode nonlinearity, limiting the achievable fractional spur suppression. The RCVS-DTC [3] uses the ACZ algorithm for non-linearity convergence; however, the ACZ is sensitive to the irregular shapes of DTC integral non-linearity (INL). To address these limitations, this work presents a 6.65-to-7.75GHz fractional-N PLL that achieves a fractional spur of -65.7dBc and an integrated jitter of 154fs at nearinteger channels. The design incorporates (i) an analog pre-distortion DTC (APD-DTC) to cancel the 2nd and 3rd-order DTC non-linearity in the time domain, and (ii) a phase detector gain (PDG) based algorithm that optimizes fractional spur levels with reduced digital resources in the background.