A 1.8V Input, 96.5% Efficiency, 4.05A/mm2 FoM, Three-Level Dual-Path Hybrid Buck Converter with Mitigated Capacitive Inrush Current and Seamless DVS Across a Wide 0.4-to-1.5V Output Range

Modern mobile SoCs increasingly demand energy-efficient, high-density power converter solutions that employ compact passive components within a small footprint, while still delivering sufficient power and retaining high efficiency. To meet these requirements, flying capacitor $(C_{\mathrm{F}})$ -assisted hybrid buck converters have been extensively explored as a viable option to reduce conduction losses $(P_{\mathrm{D}\mathrm{C}\mathrm{R}})$ associated with the higher DC resistance $(R_{\mathrm{D}\mathrm{C}\mathrm{R}})$ of miniaturized inductors [1]–[7]. In these hybrid designs, the reduction of inductor current $(/_{\mathrm{L}})$-thereby $P_{\mathrm{D}\mathrm{C}\mathrm{R}}(=R_{\mathrm{D}\mathrm{C}\mathrm{R}}\cdot I_{\mathrm{L}^{2}})$ minimization-is achieved by leveraging the current contribution from the flying capacitor $(I_{\mathrm{C}\mathrm{F},\mathrm{C}}$ to support power delivery alongside $I_{\mathrm{L}}$. However, a significant challenge remains: efficiency degradation due to surged $I_{\mathrm{C}\mathrm{F},\mathrm{C}}$ at specific voltage conversion ratios (VCRs). To mitigate this, [8] proposed an interleaved topology to relieve inrush $I_{\mathrm{C}\mathrm{F},\mathrm{C}}$, while [9] introduced a switched-capacitor design methodology optimized for a target VCR. Despite these advancements, their theoretical VCR limitations $(M=V_{\mathrm{O}} / V_{\text{IN}}>0.5$ in [8], $M < 0.4$ in [9]) restrict supplying SoC-compatible voltages from a 1.8V input $(0.22\ < M < 0.83)$. Recent research has thus focused on alleviating inrush $I_{\mathrm{C}\mathrm{F},\mathrm{C}}$ while covering a wider VCR range [10], [11]. Following this trend, this paper proposes a three-level dual-path (TLDP) hybrid buck converter that seamlessly operates across a broad VCR range $(V_{1\text{IN}} =1.8, V_{\mathrm{O}}=0.4$ to 1.5V) while effectively mitigating $I_{\mathrm{C}\mathrm{F},\mathrm{C}}$ surges. In contrast to [10], which tends to be inefficient at $M=0.5$ in terms of $I_{\mathrm{L}}$ -reduction, the proposed TLDP design maximizes the benefits of multi-path power delivery at mid-range VCRs $(M\approx 0.5)$, commonly used to power SoCs with typical $V_{\text{DD}}$ ranging from 0.6 to 1.2V.