A 0.9mm2 SDR Receiver in 40-nm CMOS Covering 10-72GHz Using Inductor-Less Based LO Quintupler

Demands for 5G NR, 6G, autopilot radar, satellite communication and other emerging applications promote the development of compact receivers for easier phased-array integration and some communication protocols such as 5G n263 require receivers with over 70GHz bands [1]–[3]. Therefore, a multi-standard-supported SDR receiver with a small die area, a high RF bandwidth and high reconfigurability shows excellent adaptation for the potential demands [4], [5]. In a multi-standard receiver, the orthogonal local oscillator (LO) accuracy directly affects the demodulation quality. However, the existing wideband orthogonal LO generators including XFMR-based 1Q network, QVCO, and hybrid-path band selection show limitations such as high core area, high power consumption, or high spur interference [6], [7]. Besides, the down-mixing scheme of RF signals over 40GHz like harmonic mixing shows relatively low conversion gain [8]. This work introduces a 10-72GHz receiver with only one inductor-less LO generator for multi-protocol applications. Phase interpolator and edge-combining switched-capacitor (SC) based frequency quintuple techniques are proposed to output 10GHz to 40GHz LOs while operating within 2-8GHz. For the 40-72GHz band, the RF signals are down-mixed two times with the same frequency to reduce the LO operating frequency to fRF/2. The first down-mixing process is performed with the image band at DC, achieving over 100dB image rejection ratio (IRR) through the transformer for input matching and then relieving the noise deterioration and image interference. This work describes a 10-72GHz, 26-48dB gain, and 19.7-23.7dBm 0lP3 SDR receiver with a 0.068mm² LO generator.