Novel Linear Model for OFF-State Stress Causing Stand-By Current of Advanced VNAND Chip

This paper presents a linear relationship between off current (Ioff) and stress time under off-state stress (OS), which had exhibited non-linear characteristics. The underlying physical mechanism was analyzed, and the reliability model was proposed from experimental results. Based on this linearity, much later evaluation results could be accurately predicted using only 1/10 times evaluations. Our approach was validated by comparing the lifetime predictions with long-term measurement data, and the error rate was less than 1%, demons trating the effectiveness of our method in reducing the evaluation time while maintaining the reliability of the results. Furthermore, we applied our model for a single transistor to a chip consisting of multiple transistors, and found the cause of chip fail by correlating them.