Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage

This study investigates the retention behavior of gate-side injection ferroelectric FETs for vertical NAND applications. Experimental results demonstrate that thicker blocking oxide layers enhance the initial memory window but result in greater retention loss at elevated temperatures due to the higher depolarization field within the ferroelectric layer. Additionally, thinner ferroelectric layers exhibit accelerated retention degradation, while thicker ferroelectric layers provide improved stability and polarization retention over time. TCAD simulations align closely with the experimental observations, providing a detailed understanding of the interplay between polarization, charge trapping, and depolarization fields. These findings offer valuable insights into optimizing layer thicknesses to enhance the retention characteristics and reliability of future vertical ferroelectric NAND storage solutions.