A-117.1dB THD Audio Decoder Utilizing Single Vector Quantizer for Simultaneous Mismatch and ISI Shaping

In high-fidelity (HiFi) audio systems, it is crucial to implement audio decoders with low-noise, high-linearity, and jitter-insensitive digital-to-analog converters (DACs) [1]–[3]. From an architectural perspective, capacitor DAC (CDAC) is less sensitive to clock jitter [4]. However, CDAC often requires low-noise and power-hungry voltage references and is vulnerable to reference noise coupling. Resistive DAC (RDAC) exhibits less flicker noise than MOS-based current sources, but RDAC calls for a low-noise reference buffer and is susceptible to routing parasitics, which result in distortion [5]. Current-steering DAC (IDAC) has low requirements for the voltage reference and is suited for area- and power-constrained audio systems. Therefore, IDAC has become the primary choice for audio decoders in recent years [1]–[3], [6]. From a circuit perspective, mismatch, inter-symbol interface (ISI), and clock jitter are the three main error sources for high-precision IDACs: 1) static mismatch error increases in-band harmonics and noise floor; 2) dynamic ISI error is converted into harmonics due to the mismatch of rise and fall switching times of the IDAC unit; 3) clock with jitter folds out-of-band noise into the audio band, thereby reducing the signal-to-noise ratio (SNR) [4].