Understanding of Incremental Step Pulse Programming (ISPP) Slope Degradation in 3D NAND and its Band-Engineered Trap Layer Solution

We propose a physical model to understand the degradation factors of incremental step pulse programming (ISPP) slope, a critical efficiency indicator for program operation in charge trap flash (CTF)-based 3D NAND Flash memory. During ISPP operation, the position of the trapped charges in the charge trap layer (CTL) significantly affects the channel surface potential, which in turn influences $\boldsymbol{V}_{\text{Th}}$. In this work, for the first time, we developed an ISPP slope model to capture the sensitivity of the channel surface potential to the position and density of charge trapped within the CTL. Our findings indicate that a major cause of ISPP slope degradation is the non-uniform trapped charge distribution within the CTL, in contrast to the uniform distribution in floating gate (FG) memory under thermal equilibrium state. Using the derived model, we successfully reproduce experimental ISPP slope and propose a band-engineered CTL to improve the ISPP slope by redistributing trapped charges.