An 83.16-TOPS/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS

Analog computing paradigms have recently been explored to reduce the energy consumption of deep neural network (DNN) processing for mobile applications. Common analog approaches employ charge sharing or current accumulation techniques within the voltage domain [1]–[8]. However, as technology scales down, voltage-domain analog computing may become less advantageous due to its limited performance gains compared to digital computing (Fig. 1, top left). In addition, lowering the supply voltage narrows the signal margin in the voltage domain, increasing noise susceptibility and leading to accuracy degradation. These challenges in technology and voltage scaling limit potential energy reduction in voltage-domain designs. In contrast, time-domain computing offers a promising alternative where data are encoded as edge timing or pulse width, with computation performed by controlling this temporal information. Time-domain computing could benefit more from technology scaling due to its digital-like behavior, commonly utilizing inverter-based delay cells. Furthermore, it maintains relatively large signal margins at lower voltages.