A Compact 28-GHz Transmitter Front End With Co-Optimized Wideband Chip–Antenna Interface

This work presents a compact 28-GHz transmitter (TX) front end implemented in 40-nm CMOS technology, along with a co-optimized wideband chip-antenna interface for wireless communication systems. The TX front end comprises a mixer and a two-stage power amplifier (PA) connected to a flipped patch antenna via bonding wires and an onboard matching network (MN). The first stage of the PA utilizes a class-C architecture with adjustable bias, which does not alter the input or load of the amplifier. By effectively introducing gain peaking to mitigate compression effects in the second stage, the overall linearity is improved. A design methodology for XF-based MNs is proposed, grounded in rigorous mathematical analysis that takes into account both matching conditions and losses, rather than relying on simulation and intuition. The onboard MN, positioned between the bonding wire from the integrated circuit (IC) and the antenna, employs a step-matching strategy to address bandwidth reduction resulting from the inductance associated with bonding wires and long transmission lines. Each TX element occupies a compact footprint of $0.7\times 0.2$ mm², facilitating seamless integration into large-scale, cost-effective wireless systems. Measurement results indicate that the TX achieves a saturation output power of 20 dBm, a 1-dB compression point (P1dB) of 18.5 dBm, and a peak drain efficiency (DE) of 30.3%, representing the highest ITRS figure of merit (FoM) to our knowledge. Notably, the PA attains an impressive power density of 1.0 W/mm². Additionally, the antenna with onboard MN exhibits a bandwidth of 4.6 GHz, further enhancing the system’s performance.