Hardware-Based Calculation of Mean Square Error for Automatic Target Recognition in SAR Images

This paper presents a circuit architecture aiming for FPGA synthesis of a processing stage of an Automatic Target Recognition (ATR) algorithm to classify non-cooperative targets in Synthetic Aperture Radar (SAR) images using the SAMPLE database. A reference algorithm in Python was used to determine whether the mathematical operations performed by the architecture are correct, comparing the results between different processing phases, such as the determination of the equivalence of coordinates between the target and the models (i.e., coordinates “matching”), partial calculations of the mean squared error, and the final result of the operations. The architecture was described in VHDL and synthesized for the Bajie Board development system with an FPGA XC7Z010-1CL400C. For a dataset of 50 coordinate points, the algorithm’s execution time in Python decreased from 4 milliseconds to approximately $30~\mu $ s in the synthesized system. Similarly, for a larger dataset of 400 coordinate points, the reduction was from 184 ms to 1.9 ms.