On-Chip Age Estimation Using Machine Learning

The semiconductor supply chain industry is spread worldwide to reduce costs and meet the high demand for integrated circuits (ICs) in electronic systems. The high utilisation of electronic devices in the next decade is forecasted to reach trillions, increasing the already high volume of e-waste. It will lead to concerns about the security and reliability of ICs, particularly those exposed to counterfeiting, i.e., recycled and remarked ICs. This paper harvests aging degradation induced by bias temperature instability (BTI) and hot carrier injection (HCI), observing frequency (f) and discharge time ( $\tau _{dv}$ ) affected by changes in drain current and sub-threshold leakage current over the lifetime of an IC to estimate the IC age. This is carried out using Cadence simulations, implementing 13- and 51-stage ring oscillators (ROs) using a 22-nm CMOS technology and aging model provided by GlobalFoundries (GF). The machine learning (ML) algorithm of support vector regression (SVR) is adapted for this application, using a training process that involves operating temperature, $\tau _{dv}$ , f, aging time and inter-die and intra-die process variation (PV). The data sampling is performed over a simulated 12-year period with representative temperatures between 20°C up to 100°C and with additional testing data from 25°C up to 75°C. Incorporating the PV effect with the SVR model allows the proposed SVR model to be adopted in practical IC implementation. The results demonstrate high accuracy in aging estimation by SVR with/without PV effects. The proposed SVR model detects the age of an IC with an error accuracy between 0.206 and 0.667 (deviation of 74.16 and 240.12 days), and 0.091 and 0.237 (deviation of 32.76 and 85.32 days) based on the Root Mean Square Error (RMSE) for 13- and 51-satge RO, respectively. It outperforms the state-of-the-art IC age prediction models even when learning and validating the model with aging and PV.