Investigating the Performance of Sub-10-nm WSi2N4 MOSFETs With Native Dielectric Through a Machine Learning Tight-Binding Framework

Monolayer WSi2N4 has emerged as a promising 2-D semiconductor for high-performance ultrascaled MOSFETs. In this work, we use machine learning techniques to generate a sparse tight-binding (TB) Hamiltonian and evaluate the performance of sub-10-nm n-type and p-type WSi2N4 MOSFETs with native Si3N4 as the gate dielectric. To validate our approach, we compare the I–V characteristics generated by our machine learning TB (MLTB) model with those obtained from a TB model using the maximally localized Wannier function (MLWF) approach for a monolayer HfS2 MOSFET, demonstrating excellent agreement. Our results show that both n-type and p-type WSi2N4 MOSFETs meet the International Roadmap for Devices and Systems (IRDS) 2022 on-current ( ${I}_{\text {on}}$ ) target for high-performance (HP) applications at channel lengths ( ${L}_{\text {ch}}$ ) of 5–10 nm. For high-density (HD) applications, n-type and p-type devices can be scaled down to 7 and 8 nm, respectively, while maintaining IRDS compliance. At a 10-nm channel length, n-type devices achieve a higher ${I}_{\text {on}}$ than p-type devices, while both exhibit comparable subthreshold swing (SS) close to the 60-mV/dec limit at room temperature. However, as ${L}_{\text {ch}}$ decreases, n-type devices experience greater SS degradation than p-type devices due to enhanced source-to-drain tunneling, allowing p-type devices to outperform at shorter channel lengths. In addition, transport simulations reveal directionally isotropic carrier behaviors in WSi2N4. These findings underline the potential of WSi2N4 for next-generation ultrascaled transistors and showcase the utility of machine-learning-based approaches in modeling devices constructed with novel 2-D materials.