An Estimation Method for Lateral Temperature Gradient on Chip Surface of Power Semiconductor Devices

Nowadays, serious lateral temperature gradient across the chip surface can significantly reduce the lifetime of the power semiconductor devices. Currently, the primary methods for extracting lateral temperature gradient on chip surface include infrared (IR) camera and finite element simulation. However, the former requires destroying the package, while the latter can be time-consuming and labor-intensive, with challenges in accuracy. In this article, the expression of lateral temperature gradient is derived. Then, influencing factors and their implications are also investigated. Finally, taking the common three types of wire-bonded power semiconductor devices for example, a method for estimating lateral temperature gradient is proposed. The effectiveness and accuracy of the method are validated by the experiment, showing agreement within 13% for discrete devices and 1% for modules. Despite validation requiring destructive package for IR measurements, subsequent applications enable nondestructive estimation through precalibrated effectiveness factors that mainly depend on the device type. In practical applications, this method helps facilitate the effective prevention or mitigation of failure risks associated with lateral temperature gradient without decapsulation. Theoretically, it contributes to advancing failure mechanism analysis and helps manufacturers improve the device reliability.