STT-HDC: An Efficient Time-Domain In-Memory Hyper-Dimensional Computing Design Based on STT-MRAM

This paper presents an efficient in-memory hyperdimensional computing (HDC) design based on spin transfer-torque magnetoresistive RAM (STT-MRAM), named STT-HDC. A novel time-domain sense amplifier circuit is proposed that significantly simplifies Hamming distance computation of HDC models while dramatically improving energy efficiency. Our design is evaluated using HSPICE simulation under the 28nm FD-SOI technology PDK (Process Design Kit). Simulation results indicate that our approach delivers an energy efficiency of 3.12(fJ) per bit, achieving a significant reduction in energy consumption relative to previous implementations. This substantial enhancement in energy performance, coupled with the simplified computation model, paves the way for more practical and scalable HDC systems in resource-constrained environments. The influence of variations in different process corners, and temperature is also thoroughly covered in the analysis.