Innovative gate driver structure achieving low time skew across isolation barrier for parallel connected SiC modules

The increasing demand for high-power density applications has driven the need for parallel connection of power transistors. However, the development of wide bandgap semiconductors introduces significant challenges in parallel operation, primarily due to the need to synchronize sharp current edges during switching. One cause of current imbalance is the delay between gate signals arise from mismatches in gate drivers. This work introduces an innovative low-jitter gate driver architecture design for eight parallel 1.2kV 204A SiC modules (ref.BSM180D12P2E002). A novel approach leverages a planar transformer with dual windings, integrating level-shifting capabilities and minimizing components responsible for jitter. A dedicated synchronization channel ensures less than 100 ps timing precision between gate signals, while a modular and flexible chained structure supports scalability to various transistor configuration. Experimental validation demonstrates the proposed architecture’s robustness across a wide temperature range (-20°C to 80°C) and its ability to achieve a maximum propagation delay skew of 5.15ns. This design represents a significant step forward in enabling efficient, high-speed switching in parallel transistor systems.