Consolidated Carrier-Based Discontinuous PWM Strategies for DC-Link Capacitance Reduction in Three-Phase Three-Level Converters

The input current distortion issue associated with discontinuous pulsewidth modulation (DPWM) is a significant concern for three-level Vienna rectifiers. While larger dc-link electrolytic capacitors can help mitigate this issue by reducing neutral-point voltage oscillations, they also lead to a substantial increase in the volume of converters. This article presents consolidated carrier-based DPWM strategies capable of mitigating input current distortion by rectifying the vector synthesis error induced by oscillated NP voltages. Therefore, even with smaller dc-link capacitances, the improved input current performance can still be preserved. Moreover, the proposed methods employ only fundamental algebraic functions, helping conserve the limited hardware resources of the digital processor. Ultimately, an experimental prototype has been constructed to corroborate the efficacy of the proposed strategies.