Edge Computing Accelerator for Real-Time Defect Detection of Photovoltaic Panel on Lightweight FPGAs

Photovoltaic (PV) panel defect detection algorithms are computationally and parametrically intensive, requiring powerful computing platforms. However, powerful computing platforms are difficult to deploy in industrial field environments, which seriously reduces the applicability of PV panel defect detection algorithms. Therefore, this article designs a real-time detection accelerator (RDA) based on field-programmable gate array (FPGA)+Acorn RISC machine (ARM) architecture. In the proposed RDA, the FPGA is utilized to implement specific accelerators for neural network operators, including components such as the operator processing unit, line buffer (LB), two-stage ping-pong buffer (TPB), and block factor (BF). The ARM processor is responsible for orchestrating the accelerator to construct the neural network. The Winograd algorithm is employed in the construction of the convolutional operator processing unit. The LBs have been designed to reduce the reuse of feature maps. The TPB is designed to improve data access bandwidth, further enhancing system throughput. To maximize FPGA on-chip resource utilization, a resource and performance optimization model is constructed, under which BF is developed. The RDA is deployed on a lightweight FPGA platform (ZYNQ7020) and evaluated using the YOLOv4-Tiny network as the baseline algorithm. The tasks of real-time detection of PV panel defects under two industrial sites (PV panel manufacturer and PV power plant) are realized. Furthermore, RDA accelerates VGG16 and YOLOv4-Tiny networks on the public datasets ultimately achieving 48.36 and 24.25 GOP/s arithmetic with 3.75- and 4.582-W power consumption on the same platform. The experimental results show that RDA has the advantages of low power consumption, high resource utilization, and low cost compared to previous FPGA accelerators.