Co-Processor Based FSM Generator

Finite State Machines (FSMs) are critical components in hardware design, particularly in modern System-on-Chips (SoCs), where their complexity and scale continue to increase in resent years, and the complexity leads to the increase of total area occupied by FSMs. In response to these demands, we present an FSM generator, a dedicated co-processor accelerator for handling FSMs within SoCs. This paper proposes an FSM generator, based on the RISC-V architecture, is highly parameterized and reconfigurable, capable of generating an optimized FSM accelerator from a flexible architectural template. Compared to a Cortex-M0-based FSM processor, Simulation results demonstrate that the speed increased by 5×, and core area consumption decreased by 3×.