FPGA-Based Testing of XOR-Free Polar Encoder

Polar codes play a pivotal role for the successor of the 5G due to their capacity-achieving approach and robust error correction performance by adapting diverse channel conditions. Polar codes use channel polarization to address critical requirements like reliability and throughput of the 5G standard. In this paper, the register transfer level (RTL) code of the polar encoder is first configured in the form of a Xilinx Vivado intellectual property (IP) block and then proposed a system-level diagram for testing that IP block using Xilinx Vivado IP Integrator. This system-level diagram sends data wirelessly between Mobile Terminal (MT) and FPGA using the Bluetooth module through the UART protocol. The system-level system is synthesized and implemented with the Zynq-7000 FPGA family using the Xilinx Vivado 2019.2 tool. Further, the functionality of the proposed RTL code for the polar encoder is validated by using a hardware-software (HW-SW) co-simulation environment created between MATLAB and Xilinx Vitis Modal Composer.