Comparison of Gate-Level Techniques for Mitigation of Single Event Transients in Combinational Logic

In this paper, the gate-level techniques for mitigation of Single Event Transients (SETs) in combinational circuits have been analyzed. The main objective was to compare the SET mitigation techniques in terms of their quantitative impact on SET generation and propagation effects for individual standard cells. The comparison was done with SPICE simulations, using the 130 nm standard cell library. The following SET mitigation techniques have been analyzed: gate upsizing, gate duplication, load upsizing, insertion of transmission gates, insertion of charge sharing logic, insertion of decoupling cells, and insertion of Schmitt trigger. We have shown that the impact of techniques based on insertion of redundant logic depends on the size of added logic and the type of target gate. In addition, we have shown that the most effective SET mitigation in logic circuits can be achieved with a combination of multiple techniques. The obtained results could serve as a guide in selection of SET mitigation approach for a given design.