Exploring Parallelism in ZynqNet AI Engine to Accelerate Image Classification in Aerospace

This research investigates various configurations of the Zynqnet AI Engine to accelerate image classification tasks using the SAT-6 dataset and a 4-layer CNN. The C++ code for the hardware accelerator was translated into RTL using Vivado HLS and integrated with the Zynq Processing System on a ZedBoard Zynq-7000 ARM/FPGA SoC. The AI engine was configured to work with 32 -bit floating point, 8bit fixed point and 8 -bit integer type operations, with different processing elements for parallelizing CNN tasks. Given a 64-bit data memory bus in communication with the accelerator and an 8-bit integer quantization, the variation in the number of processing elements does not result in a significant performance improvement. To address this, 8 values were grouped for reading and writing in 64-bit parallel mode, and different communication architectures were designed to improve data transfer between the accelerator and DDR memory, with optional enablement of L1D and L2 cache. The research analyzes CNN computation performance and FPGA resource usage (LUTs, FFs, BRAMs, DSPs) across configurations, providing insights into the trade-offs in FPGA-based CNN implementations, aiding the development of efficient, high-performance hardware accelerators for Deep Learning applications.