A Single-Source Seven-Level Modified PUC Inverter Topology with Reduced Flying Capacitors

This paper introduces a seven-level modified packed U-cell (7L-MPUC) inverter topology with reduced number of flying capacitors. The 7L-MPUC utilizes two flying capacitors rated at one-third of the DC source voltage, and employs a voltage balancing method based on an overall priority index. To show the superiority of the proposed 7L-MPUC over the state-of-the-art seven-level inverters, various comparisons have been conducted in terms of the number of switches, total blocking voltage, and flying capacitors voltages. Through detailed comparison, it is demonstrated that the proposed 7L-MPUC topology enhances the practibility by reducing flying capacitors. Simulations and experiments are presented to verify the feasibility of the proposed topology.