Performance Analysis of CMOS Full Adder Using Machine Learning

With miniaturization the design complexity of hard-ware design is increasing hence it is very important to predict the power dissipation due to the changes in design parameters of circuit components. In the era of battery operated devices, power consumption has become important challenge in order to keep long life of these devices. The simulation method is reliable and gives accurate results but it is also very time consuming. Main goal of this paper is to provide prediction of leakage power and delay promptly at early stage using machine learning(ML) algorithms so as to improve the performance of overall system. This is accomplished by using Random Forest(RF), Decision Tree(DT) and Support Vector Machine(SVM) algorithms to predict leakage power and delay of CMOS full adder circuit. Machine learning algorithms are implemented using python programming to predict leakage power and delay of full adder circuit. These predicted results are then validated with simulated results which has been obtained by simulating the circuit using NGSPICE simulator. Comparison analysis shows that, predicted values of Support Vector Machine algorithm are close to actual values. Minimum percentage error is observed between predicted and actual values of SVM model as compared to RF and DT models. Scatter plot of residual values also shows that, performance of SVM model is relatively better than RF and DT algorithms.