A Dual Slope Boosted Relaxation Oscillator With 2.93 μJ/Cycle Energy Efficiency and 0.068% Period Jitter in 180 nm CMOS

This paper presents a 2MHz relaxation oscillator designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (FIA) is adopted such that 1) the requirement of comparator speed is significantly alleviated and 2) the power consumption of the amplifier is further reduced. The proposed relaxation oscillator was fabricated in a 180nm CMOS process and occupies only 0.1mm² active area. The measurement results with 8 samples show that the average power consumption is $2.93\mu $ J/cycle ( $\mu $ W/MHz) at 1V supply voltage at room temperature. The average standard variation of the period jitter is 345ps, which is 0.068% of 500ns typical oscillation period ( $T_{\mathrm {OSC}}$ ). The measured temperature coefficient is 128ppm/°C within the 0 to 90°C range, and the voltage variation is 0.74%/0.1V from 0.95V to 1.15V. It scores a high phase noise figure-of-merit of 148dBc/Hz at 10kHz offset frequency.