A Power Grid Electromigration Test Chip for Lifetime Characterization and Model Calibration

This work presents silicon data from 28 nm test chips specifically designed to study electromigration (EM) induced lifetime effects. The power grids were generated by an automatic place-and-route tool to create realistic device-under-tests (DUT) to capture power grid EM aging behaviors and lifetimes. Poly-silicon quasi-load cells mimicking the circuit current were employed to withstand high temperature stress. 1,024 local voltages throughout the power grid were tapped out to monitor the voiding locations and IR drop trends with stress. Four power grid architectures with different metal configurations were tested under different temperatures and currents. EM effects under different temperatures and current cycling conditions were also studied.