Grouped Feature Selection for SMONs Placement in MCU Performance Screening

In safety-critical applications, microcontrollers (MCUs) must meet stringent performance requirements, particularly in terms of maximum operating frequency (Fmax). On-chip Speed Monitors (SMONs), often implemented as ring oscillators, are commonly used to determine Fmax. Previous works showed that frequency from SMONs provide valuable data for predicting Fmax via machine learning (ML) models. A common approach is to group SMONs and place them into several spots on the device. However, while increasing the number of groups can enhance predictive accuracy, it also raises production costs, power consumption, and physical area on the chip. Strategically determining the number and placement of SMON groups is therefore essential. We leverage Group Lasso regularization to selectively retain only the most informative SMONs, optimizing spatial coverage while controlling feature dimensionality and ML model accuracy. By incorporating a custom optimization metric in the model training process, this approach balances prediction accuracy with groups count, allowing for cost-effective SMON integration. Our method achieves robust performance with fewer SMONs groups, reducing production costs and silicon area requirements in the final MCU design.