Optimized 4-bit ALU Architecture for Enhanced Speed

This paper introduces an innovative, optimized design for a 4-bit ALU architecture, tackling the longstanding carry-out issue in existing architectures. Notably, our proposed design minimizes delay and power consumption using an optimized carry-out scheme with AND gates. Simulations will be performed using Cadence GPDK 90nm tool with dual power supply voltages: 4V for high-performance operations and 1.8V for low-power modes. The proposed design will be compared with the existing Mentor Graphics 130nm in terms of power consumption A comprehensive comparison of logic styles such as Pass Transistor Logic (PTL), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate Logic (TGL) reveals significant power-delay improvements. Simulation results validate our design's efficacy in resolving the carry-out issue, making it suitable for low-power, high-speed digital applications.