RAPID: Row-Access Pattern-Aware In-DRAM Prefetching

Modern computing systems face significant performance bottlenecks due to the widening gap between processor and memory speeds, known as the memory wall. This paper introduces RAPID (Row-Access Pattern-aware In-DRAM Prefetching), a novel hardware-based prefetching mechanism that leverages the internal architecture of DRAM to improve memory access efficiency. By analyzing row access patterns and performing intelligent prefetching within DRAM itself, RAPID significantly reduces memory access latency and improves over-all system performance. Our comprehensive evaluation shows that RAPID achieves an average speedup of 1.37x across a range of memory-intensive workloads compared to state-of-the-art prefetching techniques, with improvements in row buffer hit rates of up to 20%. These results demonstrate the potential of in-DRAM prefetching to address the memory wall challenge in modern computing systems.