Design and Implementation of an Efficient Quantum Cost Optimized Adder Using Reversible Logic Gates

In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.