Implementation of a Two-Channel LPC Vocoder

In this paper we describe hardware implementation of a 2400 bit/s two-channel linear predictive vocoder. The vocoder hardware uses the latest 2900 series "bit slice" microprocessor chips, and 2K RAM's and 1K ROM's of data memory. The system design is a two bus structure with a 208 ns cycle time. A significant feature of the vocoder is that it is capable of processing two voice channels simultaneously. Throughout the paper, emphasis is placed on details of firmware development of the vocoder system. Efficient design of the vocoder hardware is also discussed.