An Alternate Method to Design Digital Loop Filter of All Digital PLL using Zero Order Hold

All digital Phase locked loops (ADPLLs) are being developed as a robust alternative to analog PLLs. All the components of analog PLL are being converted into an appropriate block in the digital domain. One important block that is required to be converted from analog to digital domain is the Low pass filter. Traditionally, a Proportional-Integral (PI) based architecture is used as a digital filter. The coefficient of this architecture is derived using the bilinear transformation of the analogous analog PLL. In this work, an alternate method to derive the architecture & coefficients of the digital filter of the ADPLL is presented. It is proposed to use the Zero Order Hold (ZoH) method of transformation from s-domain to z-domain to build the LPF. Based on the resulting z-domain transfer function, the architecture of the digital filter is derived. Analytical formulae for obtaining filter coefficients are derived. A Comparison of the results of both the approaches is done. It was also found that the proposed method provides a better analytical approach for accessing the stability of the ADPLL. Lastly, a ring oscillator based ADPLL is designed in 90nm CMOS process using the proposed method and circuit simulation results are presented.