SAUN: Energy-Efficient Hardware Architecture for Systolic Array Implementation of the U-Net Model

Convolution operations in Convolution Neural Networks (CNNs) inherently offer significant data reuse potential, yet traditional Weight Stationary (WS) and Output Stationary (OS) dataflows fail to fully exploit this advantage. Furthermore, data reuse in Systolic Arrays (SAs) following the WS dataflow is restricted by the array's dimensions. To address these limitations, we propose a novel mixed dataflow approach Input Feature Map First (FF) and Channel First (CF) for Systolic Array-based U-Net (SAUN) accelerators. This architecture enhances data reuse by utilizing Weight Register Files (WRFs) in Processing Element (PE) arrays, allowing for flexible weight mapping. Furthermore, our accelerator supports both Standard Convolution (SCONV) and Transpose convolution (TCONV) operations, facilitating the reuse of input feature maps and partial sums during channel wise accumulation, thereby reducing access to on-chip SRAM.