FPGA-SoC Based Low-complexity Hardware Accelerator for Camera Pose Estimation

Camera Pose Estimation (CPE) is vital in augmented reality, virtual reality, and assisted living applications (AAL). While many software solutions exist, hardware-based solutions are more complex due to resource constraints (like memory, timing, etc.) This work uses a Field Programmable Gate Array (FPGA) based hardware accelerator to detect square binary fiducial markers for CPE, employing a single scan crack run-length algorithm for contour detection. This low-complexity method processes frames pixel by pixel, eliminating the need for buffering. High-Level Synthesis (HLS) is used for hardware development, with a co-design approach mapping fiducial detection to hardware and solving CPE via software using the Perspective-n-Point (PnP) method. The system, deployed on an FPGA-SoC, is tested on synthetic and indoor datasets. Results show successful marker detection at various resolutions and distances. The design has been prototyped and tested on a Zedboard with Xilinx Zynq®-7000 SoC.