System Synchronization Design for 4-Channel 60GSPS Data Acquisition

In modern engineering applications such as radar, communications, and physical testing, it is necessary to collect multiple pulse signals simultaneously for data inversion analysis and physical mechanism revelation. Therefore, there is an urgent need for a multi-channel high-speed synchronous data acquisition system as a support, where the sampling rate is expected to reach tens of GSPS, the bandwidth is expected to reach tens of GHz, and the synchronization accuracy between channels is expected to reach the ps level. However, the realization of such high-performance systems is a challenge for the industry. As the parallelism of high-speed acquisition systems increases, the issues of sampling clock synchronization among multiple ADCs, control synchronization among multiple FPGAs, and multi-channel acquisition synchronization have become the key issues affecting system performance. In this paper, a 4-channel synchronized data acquisition system with a sampling rate of 60GSPS is designed. First, a high-speed data acquisition scheme based on a hybrid architecture of Time Interleaving and Digital Bandwidth Interleaving (TI+DBI) is proposed according to the multi-ADC and multi-FPGA parallel sampling architecture. Then, the key technology of system synchronization implementation is introduced in detail, including multi-channel precision clock generation technology, sampling data synchronization transmission, read and write control signal synchronization transmission, and multi-channel acquisition synchronization technology. Finally, the system is fully realized through the design, debugging, and testing of specific circuits and software. The test results show that the system not only has 4 channels with a sampling rate of 60GSPS, a resolution of 12bit, and a bandwidth of 14GHz, but also the synchronization accuracy between channels can reach ±10ps. The results show that the design method proposed in this paper has high feasibility and provides a feasible design case for synchronous data acquisition design.