Analytical Model for Parasitic Resistances of Crossbar Arrays Suitable for Open-loop Programming Schemes Reliability Analysis

The stringent demands for area efficiency and low power consumption in edge devices have driven the investigation of open-loop programming schemes for In-Memory Computing (IMC) systems, which show promise for further improving energy efficiency in Artificial Intelligence (AI) applications. However, the adoption of these programming schemes requires extensive reliability analysis to ensure that signal degradation along metallization lines does not prevent the devices from reaching their target states. Unfortunately, accurate circuit simulations are impractical for AI applications due to the large number of crossbars involved, leading to infeasible simulation times. Additionally, existing analytical models of crossbar parasitic effects primarily focus on output signal degradation, overlooking the voltage drop at each cell. In this work, we modify a wellknown analytical model for parasitic resistances in resistive crossbars to provide a more accurate estimation of voltage levels at internal array nodes. The proposed model reduces the average error in estimating the voltage drop across cells during programming operations by up to $30 \%$ compared to the previous approach, while offering a significant speed-up in simulation time w.r.t. traditional SPICE analysis. Finally, we apply the model to assess two open-loop programming schemes for crossbars up to a $128 \times 128$ array, revealing reliability issues that could cause malfunctions in the IMC system if not addressed during the design phase.