Enterprise Class Modular Cache Hierarchy

The IBM Z® platform is optimized for processing vast amounts of data and transactions with low latency in a highly virtualized and secured environment. The platform and its microprocessor chip are designed to deliver consistent system performance, throughput, and response latencies with sustained processor utilization of over $\mathbf{9 0 \%}$ under all workload conditions. The IBM Telum® and IBM Telum® ${ }^{\circledR}$ II designs introduced a novel modular and scalable cache hierarchy to the industry that is extendable to future platform generations, the adoption of emerging technologies, and new architecture enhancements, all of which are required to meet the continuously evolving needs of the mission critical workloads that run on the platform. This paper demonstrates the flow of processor fetch events and how the adaptive horizontal cache persistence algorithms work in this novel design. It explores the performance and system effects of cache size changes in this architecture. Finally, the paper explores how the resulting application of solutions leveraging these effects enhances the robustness of the next generation IBM Z caching solution embedded in the IBM Telum® II Processor, which improves mission critical workload performance while simultaneously enabling the generative AI capability.