Reconfigurable Digital FPGA Implementations for Neuromorphic Computing: A Survey on Recent Advances and Future Directions

Neuromorphic computing represents hardware and software paradigms that emulate neural brain functionalities. Spiking neural networks (SNNs) are a promising brain-inspired computing approach to achieve power efficiency through event-driven processing using discrete asynchronous spikes, making them particularly effective for spatiotemporal data processing. The complex computational nature of SNNs requires intensive calculations and specialized algorithms to ensure accurate performance across different tasks. Hardware accelerators for neuromorphic computing, particularly for SNN implementations, have emerged primarily through field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). FPGAs are especially attractive for neuromorphic computing due to their flexibility, stability, programmability, reconfigurability, and rapid time to market. This research explores top-tier and well-known journal articles from the IEEE Xplore digital library and the Google Scholar databases including IEEE, ACM, Frontiers, Elsevier, Springer, MDPI, Wiley, arXiv, and Nature publishers. In this survey, various energy-efficient and high-performance FPGA implementations of spiking neurons and SNNs are reviewed. The accuracy rates of the implemented SNNs on different applications are investigated. Also, digital hardware optimization techniques for reconfigurable implementations are discussed. The synthesis results from the presented implementations are reported and compared in terms of cost (referring to utilized resources such as Registers/FFs, LUTs, Multipliers, DSP blocks, and Block RAMs), speed, and power/energy consumption. The survey concludes with recommendations for future research directions in FPGA-based neuromorphic computing.