HTV: Measuring Circuit Vulnerability to Hardware Trojan Insertion Based on Node Co-activation Analysis

Hardware Trojans (HTs) pose a significant threat to the security of integrated circuits(ICs). Measuring the vulnerability of ICs to HT insertions is crucial for enhancing design security, thereby mitigating potential security risks. This paper proposes a novel vulnerability measurement method for ICs against HT insertions based on node co-activation analysis. The method first transforms the circuit structure into a graph representation, where nodes represent circuit interconnections, and edges represent circuit components, using graph learning (GL) techniques. Next, it calculates the logical probability distribution and logic flip probability for each circuit node using simulation methods. By combining an adaptive threshold filtering strategy, the method identifies suspicious nodes in the circuit using simulation methods combined with an adaptive threshold screening strategy to identify suspicious nodes in circuits. Subsequently, it computes the joint probabilities of pairs of suspicious nodes that simultaneously exhibit rare logic values based on simulation results. Finally, the vulnerability of the circuit to HT insertions is quantified by evaluating the co-activation between pairs of suspicious nodes. Experimental results demonstrate the effectiveness, efficiency, and generalization capability of the proposed method.