Channel Coding Under Silicon Implementation Constraints

The slowdown in semiconductor technology ad-vances presents challenges for next-generation communication systems. These systems require continuous improvements in error correction performance, throughput, and energy efficiency. Although transistor density continues to follow Moore's law, there has been a notable decline in gains of interconnect delay and energy consumption. This raises two research challenges. First, data transfers contribute increasingly to the energy consumption for advanced technology nodes. Second, bridging the increasing gap between technology capabilities and demands in commu-nication systems necessitates cross-layer optimizations. In this work, we address both issues by investigating low-density parity-check (LDPC) and polar code decoder implementations. We quantify the energy consumption impact of different data transfer structures in the Tanner graph for high-throughput LDPC code decoder. Furthermore, we quantify the gains from cross-layer optimization only and the gains from technology advances only for high-throughput polar code decoders and compare them.